The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide (xe2x80x9csalicidexe2x80x9d) regions on the gate and source/drain junctions with an ultra-low silicon consumption.
In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop.
A common technique employed in the semiconductor manufacturing industry is self-aligned silicide (xe2x80x9csalicidexe2x80x9d) processing. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi2, CoSi2 and NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example, physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, DC magnetron sputtering system. Deposition is performed after both gate etch and source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, the oxide isolation, and the exposed source and drain electrodes. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG. 1.
As shown in FIG. 1, a silicon substrate 10 has been provided with the source/drain junctions 12, 14 and a polysilicon gate 16. Oxide spacers 18 have been formed on the sides of the polysilicon gate 16. The refractory metal layer 20, comprising cobalt, for example, has been blanket deposited over the source/drain junctions 12, 14, the polysilicon gate 16 and the spacers 18. The metal layer 20 also blankets oxide isolation regions 22 that isolate the devices from one another.
A first rapid thermal anneal (RTA) step is then performed at a temperature of between about 450xc2x0-700xc2x0 C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the surface of the metal, while the metal reacts with silicon and forms silicide in those regions where it comes in direct contact with the silicon. Hence, the reaction of the metal with the silicon forms a silicide 24 on the gate 16 and source/drain regions 12, 14, as depicted in FIG. 2.
After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. A second, higher temperature rapid thermal anneal step, for example above 700xc2x0 C., is applied to form a lower resistance silicide phase of the metal suicide. The resultant structure is depicted in FIG. 3 in which the higher resistivity metal silicide 24 has been transformed to the lowest resistivity phase metal silicide 26. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi2. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions so that this method is described as xe2x80x9csalicidexe2x80x9d since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
Titanium is currently the most prevalent metal used in the integrated circuit industry, largely because titanium is already employed in other areas of 0.5 micron CMOS logic technologies. In the first rapid thermal anneal step, the so-called xe2x80x9cC49xe2x80x9d crystallographic titanium phase is formed, and the lower resistance xe2x80x9cC54xe2x80x9d phase forms during the second rapid thermal anneal step. However, the titanium silicide sheet resistance rises dramatically due to narrow-line effects. This is described in European Publication No. 0651076. Cobalt silicide (CoSi2) has been introduced by several integrated circuit manufacturers as the replacement for titanium suicide. Since cobalt silicide forms by a diffusion reaction, it does not display the narrow-line effects observed with titanium silicide that forms by nucleation-and-growth. Some of the other advantages of cobalt over alternative materials such as titanium, platinum, or palladium are that cobalt silicide provides low resistivity, allows lower-temperature processing, and has a reduced tendency for forming diode-like interfaces.
One of the concerns associated with cobalt silicide technologies is that of junction leakage, which occurs when cobalt silicide is formed such that it extends to the bottom and beyond of the source and drain junctions. An example of this occurrence is depicted in FIG. 3. One source of this problem is the high silicon consumption during the salicide formation process. One way to account for the high consumption of silicon during salicide processing is to make the junctions deeper. Making the junctions deeper, however, is counter to the desire for extremely shallow source and drain junctions that support device scaling, and negatively impacts device performance.
There is a need for a method of producing ultra-shallow junctions and forming salicide in a manner that reduces the amount of silicon consumed in the junctions.
This and other needs are met by embodiments of the present invention which provide a method of forming ultra-shallow junctions in a semiconductor wafer with low silicon consumption during a salicide formation process. In this method, the gate and the source/drain junctions are first formed by doping a semiconductor material. Sidewall spacers are formed on the sidewalls of the gate. A metal layer, such as cobalt, is deposited over the gate and source/drain junctions. Disposable spacers, made of silicon nitride, for example, are formed over the metal layer where the metal layer covers the sidewall spacers. A silicon cap layer is deposited over the metal layer and the disposable spacers. Annealing is then performed to form high resistivity metal silicide regions on the gate and source/drain junctions. Unreacted portions of the silicon cap layer, the disposable spacers, and the unreacted portions of the metal layer are removed. Another annealing step converts the high resistivity metal silicide regions into low resistivity metal silicide regions.
The silicon cap layer provides a source of consumable silicon for the salicidation process, thereby reducing the amount of silicon consumed in the source/drain junctions. This maintains the advantages of ultra-shallow junctions. At the same time, salicide formation between the gate and the source/drain junctions along the sidewall spacers is prevented by the interposition of the disposable spacers between the metal layer and the silicon cap layer. The disposable spacers prevent the interaction of the metal and the silicon in this region during the annealing that forms the salicide. The reduced amount of silicon consumption permits the junctions to be made ultra-shallow and avoids creating excess junction leakage.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of forming a salicide. Semiconductor material is doped to form a gate and source/drain junctions. Amorphous regions are formed within the gate and source/drain junctions. A metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions. A consumable silicon layer is deposited over the metal layer. The metal silicide regions are formed on the gate and source/drain junctions by annealing. Formation of metal silicide regions between the gate and the source/drain junctions is prevented. In certain embodiments, the prevention involves the interposing spacers between the metal layer and the consumable silicon layer to prevent interaction of the metal layer and the consumable silicon layer in that region.
Additional features and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, when embodiments of the invention are described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modifications and various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.